//千兆转百兆输出模块
//千兆输入为GMII格式,TX_CLK=125M,data=8bit,单上升沿变化
//百兆输出为RGMII接口的百兆兼容格式,TX_CLK=25M,data=8bit(ֻ只有4bit有效,且高4bit与低4bit数据相同),单上升沿

//仅用于反馈包通过和转发 不支持其他格式的数据包
//千兆转千兆 缓存后直接过通
module phy_tx_convert_01(
		input	wire		resetb,
		input	wire		sclk,
		
		input	wire		send_flag_i,
		input	wire		pre_flag_i,
		input	wire	[7:0]	send_data_i,
		
		input	wire		send_sync,
		output	reg		send_flag,
		output	reg		pre_flag,
		output	wire	[7:0]	send_data,
		
		output	wire	[7:0]	tout
		);
			
wire	[10:0]	buf_waddr,buf_raddr;
wire		buf_wclk,buf_rclk,buf_wen;
wire	[7:0]	buf_wdata;
wire	[7:0]	buf_rdata;

reg		send_flag_i_t,pre_flag_i_t;
reg	[10:0]	in_count,send_max,pre_max;
reg		out_start_t,out_start,out_flag,ppp_flag,out_end,pre_end;
reg	[10:0]	out_count;

//*************************************************/
//		缓存BUF
//*************************************************/
phy_sram_2048_8_sdp	GMII_buf (
	.data ( buf_wdata ),
	.wraddress (buf_waddr),
	.wrclock ( buf_wclk ),
	.wren ( buf_wen ),
	
	.rdaddress (buf_raddr),
	.rdclock ( buf_rclk ),
	.q ( buf_rdata )
	);
	
assign buf_wclk		=sclk;
assign buf_wen		=send_flag_i;
assign buf_waddr	=in_count;
assign buf_wdata	=send_data_i;

assign buf_rclk		=sclk;
assign buf_raddr	=out_count;

//*************************************************/
//		输入处理
//*************************************************/
//输入信号延时
always@(posedge sclk)
	send_flag_i_t <= send_flag_i;

always@(posedge sclk)
	pre_flag_i_t <= pre_flag_i;

//输入数据计数
always@(posedge sclk)
	if (send_flag_i == 0)
		in_count <=0;
	else
		in_count <= in_count + 1;

//信号长度统计
always@(posedge sclk)
	if (send_flag_i_t == 1 && send_flag_i == 0)
		send_max = in_count - 2;
		
always@(posedge sclk)
	if (pre_flag_i_t == 1 && pre_flag_i == 0)
		pre_max = in_count - 2;
		
//*************************************************/
//		输出处理
//*************************************************/
//输入信号延时
always@(posedge sclk)
	if ((send_flag_i_t == 0) && (send_flag_i == 1))
		out_start_t <= 1;
	else
		out_start_t <= 0;

always@(posedge sclk)
	if (out_start_t == 1)
		out_start <= 1;
	else if (send_sync == 1)
		out_start <= 0;

always@(posedge sclk)
	if (send_sync == 1) begin
		if (out_start == 1)
			out_flag <= 1;
		else if (out_end == 1)
			out_flag <= 0;
		end

always@(posedge sclk)
	if (send_sync == 1) begin
		if (out_start == 1)
			ppp_flag <= 1;
		else if (pre_end == 1)
			ppp_flag <= 0;
		end

always@(posedge sclk)
	if (send_sync == 1) begin
		if (out_flag == 0)
			out_count <= 0;
		else
			out_count <= out_count + 1;
		end

always@(posedge sclk)
	if (send_sync == 1) begin
		if ((out_count == send_max) && (send_flag_i_t == 0))
			out_end <= 1;
		else
			out_end <= 0;
		end

always@(posedge sclk)
	if (send_sync == 1) begin
		if ((out_count == pre_max) && (pre_flag_i_t == 0))
			pre_end <= 1;
		else
			pre_end <= 0;
		end

always@(posedge sclk)
	send_flag <= out_flag;

always@(posedge sclk)
	pre_flag <= ppp_flag;

assign	send_data = buf_rdata;

assign	tout = 0;

endmodule